1. Field of the Invention
The present invention generally relates to memory architectures for high performance data processing systems and, more particularly, to a real-to-physical address mechanism which allows a dynamically-specified number basic storage modules (BSMs) to be a value other than a power of two, allowing higher performance for non-unit stride memory accesses, and allowing a failing BSM to be removed with only its corresponding reduction in memory space.
2. Description of the Prior Art
Due to the disparity between memory and processor speeds in a high performance data processing system, a high degree of interleaving becomes a requirement. For example, in a uni-ported vector design, a common design point is M*P interleaves, where P is the number of processors and M is the ratio of memory cycle to processor cycle. Multiple ports or pipes in a vector design increase the interleave requirements. In designs such as the Cray Y-MP computer, the number of banks is large enough that hardware constraints require a banking hierarchy. In IBM terminology, the highest level is comprised of Basic Storage Modules (BSMs). The effective number of BSMs limits the number of storage accesses allowed per processor cycle. The degree of banking within a BSM is determined by the ratio of memory to processor cycle times. As one example, there might be 64 BSMs with 128 banks each.
In most high-performance designs, the address bits are divided into the following fields: ##STR1## The first three of these fields select a memory word, while the lowest-order bits select bytes within the word. In an effort to achieve a uniform distribution of storage requests across BSM units, the BSM selection field is usually the lowest-order bits which select words. The bank selection bits are the next higher order set of bits. The remaining bits select locations within a chip and chips within a bank. For purposes of illustration, a base memory design which uses four-byte words and 64 BSMs is assumed.
Since the BSM select bits are low-order word-select bits, one failing BSM affects one word in every block of 64 words. When a BSM fails, to eliminate the gaps caused by the failing BSM, the standard approach is to use one less bit in the BSM selection field, forcing all storage requests to the "good half" of memory. This results in reducing the number of BSMs by a factor of two which, in turn, halves the available memory. An alternative to halving the number of BSMs is to provide a spare BSM which can be used to replace a failed BSM; however, the cost of an extra idle BSM is often considered unattractive.
Additionally, some high-performance memory designs have attempted to avoid the degradation which occurs when memory is referenced with a stride (or step size) which results in the set of references being confined to a small set of the memory modules. P. Budnik and D. Kuck describe the stride problem and the benefits of having a memory system in which the number of banks is not a power of two in "The organization and use of parallel memories", IEEE Trans. on Computers, vol. C-20, Dec. 1971, pp. 1566-1569 U.S. Pat. No. 4,051,551 to Duncan H. Lawrie et al. illustrates one approach to such a memory system with seventeen modules.